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Key Responsibilities and Required Skills for Analog Design Engineer

💰 $100,000 - $180,000

EngineeringHardwareAnalogMixed-SignalSemiconductor

🎯 Role Definition

As an Analog Design Engineer you will own the transistor-level design, simulation, verification and characterization of high-performance analog and mixed-signal IP and subsystems. You will translate system-level specifications into circuit architectures, deliver robust designs across PVT corners and process nodes, collaborate with layout, test, and system teams, and drive silicon bring-up and qualification. This role emphasizes hands-on SPICE simulation, strong understanding of analog physics, measurement automation, and the ability to balance trade-offs between noise, gain, bandwidth, power, and area.

📈 Career Progression

Typical Career Path

Entry Point From:

  • Junior Analog Design Engineer / Graduate Analog Engineer
  • Analog Layout Engineer or Device Modeling Engineer
  • Test, Characterization or Validation Engineer with analog focus

Advancement To:

  • Senior Analog Design Engineer
  • Staff / Principal Analog Designer
  • Analog Design Manager, Director of Analog/Mixed-Signal
  • System/SoC Architect or VP of Hardware Engineering

Lateral Moves:

  • Mixed-Signal Design Engineer (ADC/DAC/PLL expertise)
  • RF/High-Speed Analog Engineer
  • Power Management IC Designer
  • Test & Validation Lead for analog/mixed-signal products

Core Responsibilities

Primary Functions

  • Architect and implement transistor-level analog circuit designs (op-amps, comparators, integrators, current mirrors, bandgap references, LDOs, charge pumps, RF front-ends, PLLs/VCOs and ADC/DAC front-ends) that meet system-level specifications for gain, noise, linearity, dynamic range, bandwidth and power across targeted process technologies.
  • Perform detailed SPICE-level simulation (Spectre, Eldo, HSPICE or equivalent) including DC, AC, transient, noise, Monte Carlo and corner (PVT) analysis to verify performance margins and robustness under process, voltage and temperature variations.
  • Lead mixed-signal block verification: define test plans, create behavioral/RTL/Verilog-A models, run behavioral simulations, and coordinate with digital verification teams to ensure proper interaction between analog IP and digital control logic.
  • Translate system and product requirements into complete analog design specifications, key performance indicators (KPIs), and verification plans while documenting design rationale, assumptions and trade-offs for review and future reuse.
  • Collaborate closely with layout engineers to ensure matching, parasitic extraction, guard ring placement, shielding and floorplanning are compatible with schematic assumptions, and iterate on post-layout parasitic-aware simulations (PEX) to close timing and performance.
  • Deliver and maintain thorough design documentation including top-level and block-level specifications, datasheets, test procedures, measurement plans, and manufacturing release packages for tapeout and production handoff.
  • Define and execute silicon bring-up and characterization campaigns: write measurement scripts, automate instrumentation control (LabVIEW, Python, MATLAB), collect data across lots and temperature ranges, analyze results and identify root causes for failures or performance deviations.
  • Design for manufacturability, yield and reliability — implement layout strategies, redundancy and design-for-test (DFT) features, and participate in failure analysis and yield improvement initiatives with process and manufacturing teams.
  • Mentor and train junior engineers on analog design practices, simulation techniques, measurement best practices and company-specific tool flows; perform design reviews and provide constructive feedback to peer engineers.
  • Lead cross-functional design reviews with system architects, digital designers, layout, process and test teams, ensuring clear handoffs and aligning on timelines, risk mitigation and test coverage.
  • Implement low-power and power-management techniques for battery-powered and energy-constrained systems including bias optimization, switched-capacitor techniques and dynamic power gating strategies.
  • Design and validate high-speed IOs and mixed-signal interfaces (LVDS, CML, SERDES front-ends, calibration loops) including jitter/noise analysis and signal integrity considerations at the device and board level.
  • Develop and maintain automated regression suites for analog simulations and measurement analysis to accelerate design iteration cycles and ensure consistent performance tracking across process nodes and IP versions.
  • Generate and validate compact behavioral models (Verilog-A, Spectre AMS or equivalent) for integration into SoC-level simulations and early firmware development to enable system-level verification before silicon.
  • Evaluate transistor-level impacts of advanced process nodes (e.g., 65nm, 28nm, 22nm, FinFET nodes) and alternative technologies (BiCMOS, SiGe) on analog performance; adapt circuit topologies and biasing techniques to accommodate scaled device physics.
  • Drive root-cause analysis for silicon issues by combining measurement data, post-layout simulations, and statistical analysis to produce corrective action plans and design fixes for subsequent silicon iterations.
  • Specify and select test equipment and automated measurement platforms (oscilloscopes, network analyzers, spectrum analyzers, precision source-measure units, probe stations) and define calibration procedures to guarantee measurement accuracy.
  • Balance design trade-offs among noise, offset, linearity, power, startup behavior and stability margins — produce sensitivity analyses and propose pragmatic design compromises aligned with product cost and schedule goals.
  • Participate in IP reuse and standard-cell analog library development, contributing analog building blocks, test structures and characterization data to accelerate future designs and reduce NRE.
  • Ensure analog designs meet regulatory and robustness requirements (ESD protection, latch-up immunity, input protection networks) and support product qualification for temperature, vibration, acceleration and lifespan testing.
  • Support firmware and system software teams in developing calibration algorithms and compensation routines for analog front-ends and sensors, providing characterization data and model parameters.
  • Interface with external foundries and IP vendors to coordinate process development, PDK issues, and third-party analog IP integration, including evaluation of vendor datasheets and characterization reports.
  • Drive continuous improvement of analog design methodologies, tool flows and documentation standards to shorten design cycles while maintaining quality and first-pass silicon success rates.
  • Contribute to project scheduling, resource planning and risk mitigation by providing accurate effort estimates for analog blocks and proactively reporting design status, technical risks and mitigation plans.

Secondary Functions

  • Support ad-hoc measurement requests and troubleshooting for system-level integration tasks, providing rapid prototyping and testbed assistance.
  • Partner with system architects and firmware teams to refine product-level specifications based on silicon behavior, measurement feedback and customer requirements.
  • Assist in creating training materials, internal knowledge base articles and best-practice repositories for analog design patterns and measurement techniques.
  • Participate in cross-functional problem-solving sessions to resolve customer escalations, post-silicon bugs, and field issues related to analog performance.
  • Contribute to corporate IP strategy by identifying reusable analog blocks and defining roadmaps for IP hardening and qualification across process nodes.

Required Skills & Competencies

Hard Skills (Technical)

  • Transistor-level analog design expertise: operational amplifiers, comparators, bandgap references, LDOs, charge pumps, current references, sense amplifiers and passive networks.
  • Strong SPICE simulation skills (Cadence Spectre, HSPICE, Synopsys Eldo) for DC, AC, transient, noise, Monte Carlo and corner analysis.
  • Mixed-signal verification experience and ability to write or consume behavioral models (Verilog-A, SystemVerilog-AMS) and create testbenches.
  • Cadence Virtuoso schematic entry, layout editing and PEX workflow; familiarity with DRC/LVS flows and parasitic extraction.
  • Measurement and characterization proficiency with oscilloscopes, network/spectrum analyzers, precision SMUs, signal generators, probe stations and automated test stands.
  • Familiarity with test automation and data analysis tools: Python (numpy/pandas/matplotlib), MATLAB, LabVIEW, and scripting for instrument control (SCPI).
  • Experience with ADC/DAC, PLL/VCO design and calibration, as well as techniques for jitter, phase noise and matching analysis.
  • Knowledge of process technologies (CMOS, BiCMOS, SiGe) and how device physics at different nodes impact analog design choices.
  • Experience performing yield, reliability and failure analysis; knowledge of DFT strategies for analog and mixed-signal ICs.
  • Proficiency creating datasheets, test plans, silicon release packages and formal design documentation for production handoff.
  • Familiarity with PCB-level considerations for analog blocks: decoupling, grounding, layout constraints, package parasitics, and signal integrity.
  • Experience with EDA tool automation, regression scripting and version control workflows for analog designs.

Soft Skills

  • Excellent written and verbal communication for conveying complex analog concepts to multidisciplinary stakeholders (layout, digital, firmware, product).
  • Strong problem-solving and diagnostic skills; methodical approach to root-cause analysis and data-driven decisions.
  • Collaborative team player who can lead cross-functional design reviews and work effectively with remote/global teams.
  • Mentoring and coaching capability to develop junior engineers; constructive feedback and process stewardship.
  • Time management and prioritization skills in a fast-paced development environment with multiple competing deadlines.
  • Adaptability to changing product requirements and willingness to iterate designs quickly while maintaining rigor.

Education & Experience

Educational Background

Minimum Education:

  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, Applied Physics or closely related field.

Preferred Education:

  • Master’s or PhD in Electrical Engineering or Microelectronics with a concentration in analog/mixed-signal circuit design, semiconductor devices or integrated circuits.

Relevant Fields of Study:

  • Electrical Engineering (Analog / Mixed-Signal / Microelectronics)
  • Applied Physics (Solid-state devices)
  • Semiconductor Engineering
  • Computer Engineering (with strong analog focus)

Experience Requirements

Typical Experience Range: 3–12+ years of professional analog or mixed-signal IC design experience depending on seniority level.

Preferred:

  • 5+ years designing and shipping analog/mixed-signal IP in commercial semiconductor processes, with demonstrated silicon bring-up and characterization experience.
  • Proven track record of first-pass silicon success or rapid root-cause fixation cycles on multiple tapeouts.
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